Design of Low Power Efficient CMOS Dynamic Latch Comparator
نویسنده
چکیده
High performance analog to digital converters (ADC), memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators.SAR-ADC is best suited for low power applications where power has a trade-off with speed.Comparator is one of the core components of SAR-ADC that introduces error voltage due to mismatch and consumes large power. This work presents the analysis of various dynamic latch comparators which are there in market and a new comparator has been designed which is optimized to achieve smaller size and less power. The proposed comparators have been designed and simulated using 130nm CMOS 1P2M technology by using mentor graphics tools with a supply voltage of 1V.
منابع مشابه
Analysis and Design of Low Power High Speed Dynamic Latch Comparator using CMOS Process
This paper presents the need for ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intu...
متن کاملLow Power CMOS Dynamic Latch Comparator using 0.18μm Technology
The design and analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation. Simulation results are obtained in 0.18um with supply voltages of 1....
متن کاملDesign Of High Performance CMOS Dynamic Latch Comparator
High performance analog to digital converters (ADC), memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators. This paper presents an ameliorate design for a dynamic latch based comparator in attaining high performance. The comparators accuracyis mainly defined by two fa...
متن کاملSimulation of Different Characteristics of CMOS Charge Sharing Dynamic Latch Comparator in 0.35μm, 0.25μm and 0.18μm Technologies
Abstract — The design and various analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation, offset with high ICMR. Simulation results are obt...
متن کاملDesign of power-efficient adiabatic charging circuit in 0.18μm CMOS technology
In energy supply applications for low-power sensors, there are cases where energy should be transmitted from a low-power battery to an output stage load capacitor. This paper presents an adiabatic charging circuit with a parallel switches approach that connects to a low-power battery and charges the load capacitor using a buck converter which operates in continuous conduction mode (CCM). A gate...
متن کامل